Memory devices are typically provided as internal storage areas in a computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Memory devices that do not lose the data content of their memory cells when power is removed are generally referred to as non-volatile memories. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having charge storage nodes, such as floating gates or charge traps, for example. Data is stored in the floating gate field effect transistor (FET) memory cells in the form of charge on the charge storage node. One type opf charge storage node, a floating gate, is typically made of doped polysilicon disposed over the channel region and electrically isolated from the other cell elements by a dielectric material, typically an oxide. Charge is transported to or removed from the floating gate or trapping layer by specialized programming and erase operations, respectively, altering the threshold voltage of the device.
Yet another type of non-volatile memory is a Flash memory. A typical Flash memory comprises a memory array, which includes a large number of charge storage node based memory cells. The cells are usually grouped into sections called “erase blocks.” Each of the cells within an erase block can be electrically programmed by tunneling charges to its individual charge storage node. Unlike programming operations, however, erase operations in Flash memories typically erase the memory cells in bulk erase operations, wherein all memory cells in a selected erase block are erased in a single operation. It is noted that in recent non-volatile memory devices multiple bits have been stored in a single cell by utilizing multiple threshold levels or a non-conductive charge trapping layer with the storing of data trapped in a charge near each of the sources/drains of the memory cell FET.
A NAND architecture array of a EEPROM or Flash also arranges its array of non-volatile memory cells in a matrix of rows and columns, as a conventional NOR array does, so that the gates of each non-volatile memory cell of the array are coupled by rows to word lines (WLs). However, unlike NOR, each memory cell is not directly coupled to a source line and a column bit line. Instead, the memory cells of the array are arranged together in strings, typically of 8, 16, 32, or more each, where the memory cells in the string are coupled together in series, source to drain, between a common source line and a column bit line. It is noted that other non-volatile memory array architectures exist, including, but not limited to AND arrays, OR arrays, and virtual ground arrays.
In modern NAND flash memories, NAND array density is increasing. Array pitch-pattern is getting smaller as each new generation of fabrication processes advances. Because of increasing array density, array-related area uses up a great deal of die space, and can potentially be more than a die package like a thin small online package (TSOP) memory housing.
As a result of advancing process technologies, the defect rate in array-related areas is likely to increase because of very tight data line (such as those data lines typically referred to as bit lines) to data line pitch. For example, bit line decoding in increased-density arrays typically has a high defect rate.
Newer forms of NAND flash compensate for these difficulties by replacing a high voltage transistor for bit line decoding with a lower voltage transistor in order to decode bit line groups, such as even and odd pages. Such lower voltage transistors, often referred to as low voltage transistors (NMOS or PMOS types, for example), are smaller in physical size than, and operate at lower voltages than, larger, higher power transistors. Bit lines are typically charged to near 20 volts during an erase operation. In such erase operations, the low voltage transistor, typically a select-gate n-type metal oxide semiconductor, is also charged to a higher voltage so that it does not break down. Breakdown of such a low voltage transistor can trap a high voltage on the bit lines.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for erasing memory blocks without low voltage transistor breakdown.